Switching controller for power sharing of parallel power supplies

ABSTRACT

A switching controller for power sharing of power supplies is disclosed. The switching controller includes an input circuit coupled to an input terminal to receive an input signal for generating a phase-shift signal, a first integration circuit coupled to the input circuit to generate a first integration signal in response to a pulse width of the input signal, and a control circuit coupled to the first integration circuit to generate a switching signal for switching the power supply, wherein the switching signal is enabled in response to the phase-shift signal, and a pulse width of the switching signal is determined in accordance with the first integration signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to switching controllers, and moreparticularly to a switching controller of parallel power supplies.

2. Description of the Related Art

In order to fulfill the high-speed need for computer and communicationsystems, a power supply is required to deliver more current to CPU andits peripherals. However, such a high current demand increases powerlosses in the power supply. The power loss of the power supply isproportional to the square of its switching current.P _(LOSS) =I ² ×R  (1)

where I is the switching current of the power supply, and R is theimpedance of the switching devices such as the resistance of theinductor and the transistor, or the like.

Higher output current results in lower efficiency and the efficiency ismore adversely affected for the power supply with low output voltage. Inrecent development, parallel-output technologies have been developed tosolve this problem. Examples are, for instance, “DC-to-DC controllerhaving a multi-phase synchronous buck regulator”, U.S. Pat. No.6,262,566 to Dinh; “Multi-phase converter with balanced currents” byWalters et al., U.S. Pat. No. 6,278,263; “Multi-phase switchingconverters and methods” by Ashburn et al., U.S. Pat. No. 6,362,608 and“Multi-phase and multi-module power supplies with balanced currentbetween phases and modules” by Yang et al., U.S. Pat. No. 6,404,175.However, one problem of these prior arts is the limited parallelchannels. Typically, mere two or three channels are developed in termsof the disclosures of the prior art. The limited parallel channels causeinflexibility of the application of the parallel-output technologies,especially for off-line power supplies. Another disadvantage is thebalance current approach that requires the measurement of the switchingcurrent. The switching current measurement normally causes power losses.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a switchingcontroller with power sharing capability for parallel power suppliesthat requires no current measurement and enhances flexibility ofapplication of parallel channels.

In order to achieve the above and other objectives, the switchingcontroller for parallel power supplies according to the presentinvention comprises an input circuit to receive an input signal forgenerating a phase-shift signal, a resistor determining a delay time inbetween the input signal and the phase-shift signal, a first integrationcircuit coupled to the input circuit to generate a first integrationsignal in response to a pulse width of the input signal, and a controlcircuit to generate the switching signal for switching the power supply.The switching controller for a power supply further comprises a secondintegration signal for generating a second integration signal inresponse to a pulse width of a switching signal.

The switching signal is enabled in response to an enabling of thephase-shift signal, and is disabled in response to the comparison of thefirst integration signal and the second integration signal. The timeconstant of the first integration circuit is correlated with the timeconstant of the second integration circuit. Therefore, the pulse widthof the switching signal is determined in accordance with the level ofthe first integration signal. The level of the first integration signalis increased in response to the increase of pulse width of the inputsignal, while the pulse width of the switching signal is decreased inresponse to the decrease of the integration signal. The pulse width ofthe switching signal will be same as the pulse width of the input signalto achieve the power sharing. Furthermore, a detection circuit isprovided to detect the input signal, allowing the switching signal to beenabled in response to a pulse signals if the input signal were detectedby the detection circuit to be not available. An oscillator is furtherprovided to generate the pulse signal and a ramp signal, and a feedbackterminal is coupled to the output of the power supply to receive afeedback signal. It allows the switching signal is disabled in responseto the comparison of the feedback signal and the ramp signal.

The switching controller with power sharing capability of the presentinvention can be stand-alone or parallel operation to provide highoutput current for power supply. The number for the parallel arrangementof the switching controller has no limit theoretically. Synchronizationand phase shift can be further utilized to spread switching noise andreduce ripple. As power sharing is used instead of the balance current,no current measurement is needed, which simplifies the circuit andfurther improves the efficiency of power supply.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

FIG. 1 shows a preferred embodiment of parallel power supplies accordingto present invention.

FIG. 2 shows a switching controller according to present invention.

FIG. 3 shows a power sharing circuit of the switching controlleraccording to present invention.

FIG. 4 is a preferred embodiment of an input circuit according topresent invention.

FIG. 5 shows a circuit schematic of a pulse generator.

FIG. 6 is a detection circuit for detecting the input of the inputsignal.

FIG. 7 shows an integration circuit according to present invention.

FIG. 8 shows an oscillation circuit.

FIG. 9 shows a circuit schematic of a multiplexer.

FIG. 10 shows a reset circuit according to present invention.

FIG. 11 shows key waveforms of the switching controller according to,present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a preferred embodiment of parallel power supplies accordingto present invention. A switching controller 10, a transistor 12 and atransformer 15 develop a first power converter. The output terminal SWof the switching controller 10 is coupled to control the transistor 12.The transistor 12 is used for switching the transformer 15. A rectifier16 and a capacitor 17 are connected to the transformer 15 to generatethe output for the first power converter. A switching controller 20, atransistor 22 and a transformer 25 develop a second power converter. Arectifier 27 and a capacitor 27 are connected to the transformer 25 togenerate the output of the second power converter. A switchingcontroller 40, a transistor 42 and a transformer 45 develop a fourthpower converter. A rectifier 46 and a capacitor 47 are connected to thetransformer 45 to produce the output of the fourth power converter. Theoutput of the first power converter, the output of the second powerconverter and the output of the fourth power converter are parallelconnected to the output voltage V_(O) of the power supply. Thetransformer 15 is coupled to an input voltage V_(IN). When the switchingcontroller 10 is on, a switching current I_(10-sw) is generated. It isgiven by,

$\begin{matrix}{I_{10 - {SW}} = {\frac{V_{IN}}{L_{15}} \times T_{{ON} - 10}}} & (2)\end{matrix}$

where the L₁₅ is the inductance of the primary winding of thetransformer 15; T_(ON-10) is the on time of the switching controller 10;V_(IN) is the input voltage.

The feedback terminal FB of the switching controller 10 is coupled tothe output voltage V_(O) through the feedback circuit 50 to regulate theoutput voltage V_(O) of the power supply. The feedback circuit 50normally includes an error amplifier and an optical coupler to generatea feedback signal V_(FB) is response to the output voltage V_(O) of thepower supply. The output terminal SW of the switching controller 10 iscoupled to the input terminal SYN of the switching controller 20. Itsprevious switching controller controls the switching controller 40through the input terminal SYN. A resistor 21 is connected to theswitching controller 20 to determine the delay time between switchingsignals of the switching controller 10 and 20. A resistor 41 isconnected to the switching controller 40 to determine the delay timebetween switching signals of the switching controller 40 and itsprevious controller. The switching controller 10 is operated as a mastercontroller, while the switching controllers 20 and 40 are activated asslave controllers. The output of power converters is connected to theoutput voltage V_(O). Slave controllers can be connected as a daisychain for the synchronization and power sharing. The on-time and theswitching period of slave controllers will follow the on-time and theswitching period of the master controller.

The output power P_(O) of the power supply can be expressed as,

$\begin{matrix}{P_{O} = {\frac{1}{2} \times L \times I^{2}}} & (3) \\{P_{10} = \frac{\left( V_{IN} \right)^{2} \times \left( T_{{ON} - 10} \right)^{2}}{2 \times L_{15} \times T_{10}}} & (4) \\{P_{20} = \frac{\left( V_{IN} \right)^{2} \times \left( T_{{ON} - 20} \right)^{2}}{2 \times L_{25} \times T_{20}}} & (5) \\{P_{40} = \frac{\left( V_{IN} \right)^{2} \times \left( T_{{ON} - 40} \right)^{z}}{2 \times L_{45} \times T_{40}}} & (6) \\{P_{O} = {P_{10} + P_{20} + \ldots + P_{40}}} & (7)\end{matrix}$

where L₂₅ and L₄₅ is the inductance of the transformer 25 and 45respectively; T_(ON-20) and T_(ON-40) is the on time of the switchingcontroller 20 and 40 correspondingly; T₁₀, T₂₀ and T₄₀ are switchingperiod of the switching controller 10, 20 and 40; P₁₀ is the outputpower of the first power converter; P₂₀ is the output power of thesecond power converter; P₄₀ is the output power of the fourth powerconverter.

Because the on-time and the switching period of the slave controllersare designed equal to the on-time T_(ON) and the switching period T ofthe master controller, the output current of each power converter willbe same if the inductance of the transformer is similar.

FIG. 2 shows a preferred embodiment of the switching controlleraccording to the present invention. The switching controller includes apower-sharing circuit (PSC) 100 connected to the input terminal SYN forreceiving the input signal S_(YN), allowing the input signal SYN to bethe output signal of another switching controller. The power sharingcircuit (PSC) 100 is also coupled to an input terminal DLY to receive aninput current I_(DLY). The resistor such as the resistor 21 or 41determines the input current I_(DLY). The power-sharing circuit (PSC)100 is used to generate a phase-shift signal S₂, a control signal CNTand a first integration signal V_(T) in response to the input signalS_(YN). The phase-shift signal S₂ is generated after a delay timeT_(DLY) when the input signal S_(YN) is enabled. The input currentI_(DLY) determines the delay time T_(DLY). The control signal CNTindicates the availability of the input signal S_(YN). The firstintegration signal V_(T) is produced in accordance with the pulse widthof the input signal S_(YN).

An oscillator (OSC) 200 is utilized to generate a pulse signal PLS and aramp signal RAMP. The pulse signal PLS and the phase-shift signal S₂ areconnected to a multiplexer (MUX) 250. The control signal CNT isconnected to control the multiplexer 250. The multiplexer (MUX) 250outputs the phase-shift signal S₂ when the control signal CNT isenabled. The multiplexer (MUX) 250 will output the pulse signal PLS ifthe control signal CNT is disabled. The output signal ON of themultiplexer (MUX) 250 is coupled to set a flip-flip 80. The flip-flop 80and an AND gate 85 form a control circuit to generate a switching signalPWM at the output of the AND gate 85. Inputs of the AND gate 85 areconnected to the output of the flip-flop 80 and the output of themultiplexer (MUX) 250. The flip-flop 80 is reset by a reset signal OFF.A reset circuit 300 is developed to generate the reset signal OFF inresponse to the first integration signal V_(T) or the feedback signalV_(FB). When the control signal CNT is disabled, the reset signal OFF isgenerated in response to the feedback signal V_(FB). The feedback signalV_(FB) compares with the ramp signal RAMP to generate the reset signalOFF. The control signal CNT is disabled when the switching controller isoperated as the master controller. If the switching controller isoperated as the slave controller, the control signal CNT will be enabledand the reset signal OFF will be generated in response to the firstintegration signal V_(T). The switching signal PWM is coupled to theoutput SW of the switching controller through a drive circuit 90.

FIG. 3 shows the power sharing circuit 100. It includes an input circuit110 and a first integration circuit (INT) 160. The input circuit 110 iscoupled to the input terminal SYN and the input terminal DLY to receivethe input signal SYN and the input current I_(DLY) for generating thecontrol signal CNT, the phase-shift signal S₂ and an input-shapingsignal S₁. The input-shaping signal S₁ is connected to the firstintegration circuit (INT) 160. The first integration circuit (INT) 160generates the first integration signal V_(T) in response to theinput-shaping signal S₁ and the switching signal PWM.

FIG. 4 is a preferred embodiment of the input circuit 110. A buffer gate130 is connected to the input terminal SYN to receive the input signalS_(YN). The buffer gate 130 generates the input-shaping signal S₁ inresponse to the input signal S_(YN). The input-shaping signal S₁ will beenabled (logic-high) when the input signal S_(YN) is higher than thethreshold voltage of the buffer gate 130. An operational amplifier 115having a positive input connected a reference voltage V_(REF). Thenegative input of the operational amplifier 115 is coupled to the inputterminal DLY. The operational amplifier 115 associates with a transistor120 generate a current 1120 in accordance with the resistance of theresistor such as the resistor 21 or 41. Transistors 121 and 122 form acurrent mirror to generate a current 1122 in accordance with the currentI₁₂₀. The current I₁₂₂ is connected to charge the capacitor 125. Theinput of a buffer gate 131 is connected to the capacitor 125. The outputof the buffer gate 131 is connected to an input of an NAND gate 132.Another input of the NAND gate 132 is connected to the input-shapingsignal S₁. The output of the NAND gate 132 is coupled to generate thephase-shift signal S₂ through a pulse generator 135. The delay timeT_(DLY) is thus existed in between the enabling of the input signalS_(YN) and the enabling of the phase-shift signal S₂. The resistor suchas resistor 21 or 41 determines the current I₁₂₀ and the current I₁₂₂.The current I₁₂₂ and the capacitance of the capacitor 125 determine thedelay time T_(DLY).

A transistor 117 is connected to the capacitor 125 to discharge thecapacitor 125. An NAND gate 133 is applied to control the on/off of thetransistor 117. The first input of the NAND gate 133 is theinput-shaping signal S₁. The second input of the NAND gate 133 isconnected to the switching signal PWM via an inverter 134. Therefore,the capacitor 125 is discharged once the input-shaping signal S₁ isdisabled or the switching signal PWM is enabled. Furthermore, adetection circuit 140 is utilized to detect the input of the inputsignal SYN. The detection circuit 140 will generate the control signalCNT in response to the phase-shift signal S₂.

FIG. 5 shows the circuit schematic of the pulse generator 135. Aninverter 151 is connected to the input of the pulse generator 135 toreceive an input signal. The output of the inverter 151 is coupled tocontrol a transistor 153 through an inverter 152. A capacitor 155 isparallel connected with the transistor 153. A current source 150 iscoupled to charge the capacitor 155. An inverter 157 is connected to thecapacitor 155. The output of the inverter 157 is connected to an inputof an AND gate 159. Another input of the AND gate 159 is connected tothe output of the inverter 151. The output of the AND gate 159 isconnected to the output of the pulse generator 135. Therefore, the pulsegenerator 135 generates a pulse voltage in response to the falling edgeof the input signal of the pulse generator 135. The current of thecurrent source 150 and the capacitance of the capacitor 155 determinethe pulse width of the pulse voltage.

FIG. 6 is the detection circuit 140. The phase-shift signal S₂ iscoupled to control a transistor 142. The transistor 142 is used todischarge a capacitor 145. A current source 143 is connected to chargethe capacitor 145. The input of an inverter 147 is connected to thecapacitor 145. The output of the inverter 147 is connected to reset aflip-flop 149. The flip-flop 149 is enabled by the phase-shift signalS₂. The flip-flop 149 is used to generate the control signal CNT inresponse to the phase-shift signal S₂. If the phase-shift signal S₂ isnot inputted within a time-out period, the control signal CNT will bedisabled. The current of the current source 143 and the capacitance ofthe capacitor 145 determine the time-out period.

FIG. 7 shows a preferred embodiment of the first integration circuit160. A current source 180 is connected to charge a capacitor 185 througha switch 190. The switch 190 is controlled by the input-shaping signalS₁. A capacitor 186 is coupled to the capacitor 185 via a switch 191.The switch 191 is controller by a first-sample signal S_(P1). Acapacitor 187 is coupled to the capacitor 186 through a switch 192 togenerate the first Integration signal V_(T). The switch 192 iscontroller by a second-sample signal S_(P2). The second-sample signalS_(P2) is generated by the switching signal PWM through a pulsegenerator 165. A pulse generator 170 is used to generate thefirst-sample signal S_(P1) in response to the input-shaping signal S₁. Atransistor 181 is connected to discharge the capacitor 185 in responseto the end of the first-sample signal S_(P1). The first-sample signalS_(P1) is coupled to control the transistor 181 through a pulsegenerator 175. Therefore, the pulse width T_(ON1) of the input signalS_(YN), the current I₁₈₀ of the current source 180 and the capacitanceC₁₈₅ of the capacitor 185 determine the level of the first integrationsignal V_(T).

$\begin{matrix}{V_{T} = {\frac{I_{180}}{C_{185}} \times T_{{ON}\; 1}}} & (8)\end{matrix}$

FIG. 8 shows the circuit schematic of the oscillator 200. A currentsource 210 is coupled to charge a capacitor 220 via a switch 211. Acurrent source 215 is coupled to discharge the capacitor 220 via aswitch 216. A comparator 230 includes a trip-point voltage V_(H). Acomparator 231 includes a trip-point voltage V_(L). Comparators 230 and231 are coupled to detect the voltage of the capacitor 220. NAND gates235 and 236 form a latch circuit. The output of the comparator 230 andthe output of the comparator 231 are connected to the latch circuit. Theoutput of the latch circuit is connected to the input of an NAND gate237. The output of the NAND gate 237 is connected to an inverter 240,which generates the pulse signal PLS. The pulse signal PLS is furthercoupled to control the on/off of the switch 216. The output of the NANDgate 237 is used to control the switch 211. The control signal CNT isutilized to discharge the capacitor 220 through a transistor 225 oncethe control signal CNT is enabled. The control signal CNT is furtherconnected to disable the pulse signal PLS through an inverter 241 andthe NAND gate 237. FIG. 9 shows the circuit schematic of the multiplexer250. An AND gate 252 is connected to receive the pulse signal PLS. AnAND gate 253 is connected to receive the phase-shift signal S₂. Thecontrol signal CNT is connected to AND gate 253. The control signal CNTis further connected to the AND gate 252 via an inverter 251. An NORgate 256 is used to generate the output signal ON of the multiplexer 250in response to the output of AND gates 252 and 253.

FIG. 10 shows a preferred embodiment of the reset circuit 300. The resetcircuit 300 includes a second integration circuit 310, comparators 330,345, an NOR gate 370, AND gates 351, 352 and inverters 360, 361. Thesecond integration circuit 330 contains a current source 320, acapacitor 325, a transistor 316 and an NAND gate 315. The switchingsignal PWM and the control signal CNT are connected to NAND gate 315.The output of NAND gate 315 is coupled to discharge the capacitor 325through the transistor 316. The current source 320 is coupled to chargethe capacitor 325 once the switching signal PWM and the control signalCNT are enabled. A second integration signal SAW is generated inresponse to the enabling of the switching signal PWM. The secondintegration signal SAW is connected to the comparator 330 to comparewith the first integration signal V_(T). The output of the comparator330 is coupled to generate the reset signal OFF through the AND gate 351and the NOR gate 370. Therefore, the switching signal PWM will bedisabled once the second integration signal SAW is higher than the firstintegration signal V_(T). The pulse width T_(ON2) of the switchingsignal PWM can be expressed as,

$\begin{matrix}{T_{{ON}\; 2} = {\frac{C_{325}}{I_{320}} \times V_{T}}} & (9)\end{matrix}$where the C₃₂₅ is the capacitance of the capacitor 325; I₃₂₀ is thecurrent of the current source 320. Refer to equation 8, the equation 9can be written as,

$\begin{matrix}{T_{{ON}\; 2} = {\frac{C_{325}}{I_{320}} \times \frac{I_{180}}{C_{185}} \times T_{{ON}\; 1}}} & (10)\end{matrix}$Select the capacitance C₃₂₅ correlated to the capacitance C₁₈₅. Set thecurrent I₃₂₀ correlated to the current I₁₈₀. The pulse width T_(ON2) ofthe switching signal PWM will be same as the pulse width T_(ON1) of theinput signal S_(YN). Therefore, the first integration signal V_(T) isincreased in response to the increase of pulse width T_(ON1) of theinput signal S_(YN). The pulse width T_(ON2) of the switching signal PWMis decreased in response to the decrease of the first integration signalV_(T).

The output of the comparator 345 is connected to the AND gate 352.Anther input of the AND gate 352 is coupled to the control signal CNTthrough the inverter 360. The second input of the NOR gate is connectedto the output of the AND gate 352. The feedback signal V_(FB) and theramp signal RAMP are coupled to the comparator 345 to generate the resetsignal OFF signal when the control signal CNT is disabled. The thirdinput of the NOR gate is coupled to a power-on reset signal PWRSTthrough the inverter 361.

FIG, 11 shows waveforms of the input signal S_(YN) and the switchingsignal PWM, The input signal S_(YN) is coupled to generate the switchingsignal PWM after the delay time T_(DLY). The first integration signalV_(T) is generated in accordance with the pulse width T_(ON1) of theinput signal S_(YN). Once the switching signal PWM is generated, thesecond integration signal SAW will be generated accordantly. Theswitching signal PWM will be disabled once the second integration signalSAW is higher than the first integration signal V_(T). The pulse widthT_(ON2) of the switching signal PWM is thus same as the pulse widthT_(ON1) of the input signal S_(YN). The power sharing is thereforeachieved for parallel power converters.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims or their equivalents.

1. A switching controller for power sharing of parallel power supplies,the switching controller comprising: an input circuit coupled to aninput terminal to receive an input signal for generating a phase-shiftsignal; a first integration circuit coupled to the input circuit togenerate a first integration signal in response to a pulse width of theinput signal; a control circuit coupled to the first integration circuitto generate a switching signal for switching the power supply; anoscillator generating a pulse signal and a ramp signal; and a feedbackterminal coupled to an output of the power supply to receive a feedbacksignal; wherein if the input signal is not available, the switchingsignal is enabled in response to the pulse signal, and is disabled inresponse to a comparison of the feedback signal and the ramp signal, andwherein the switching signal is enabled in response to the phase-shiftsignal, and a pulse width of the switching signal is determined inaccordance with the first integration signal.
 2. The switchingcontroller as claimed in claim 1, further comprising a resistor fordetermining a delay time between an enabling of the input signal and anenabling of the phase-shift signal.
 3. The switching controller asclaimed in claim 1, wherein the first integration signal is increased inresponse to an increase of the pulse width of the input signal, and thepulse width of the switching signal is decreased in response to adecrease of the first integration signal.
 4. The switching controller asclaimed in claim 1, wherein the input circuit comprises a detectioncircuit to detect an input of the input signal.
 5. The switchingcontroller as claimed in claim 1 further comprising a second integrationcircuit coupled to generate a second integration signal in response tothe pulse width of the switching signal, wherein the input circuitfurther generates another phase-shift signal, and the switching signalis disabled in response to a comparison of the first integration signaland the second integration signal.
 6. The switching controller asclaimed in claim 1, wherein the phase-shift signal is generated after adelay time when the input signal is enabled.
 7. A power sharing circuitfor parallel power supplies, the switching controller comprising: aninput circuit for receiving an input signal and generating a phase-shiftsignal; a first integration circuit coupled to the input circuit forintegrating the input signal and generating a first integration signal;a control circuit coupled to the input circuit and enabled in responseto the input signal to generate a switching signal; a second integrationcircuit coupled to the control circuit for integrating the switchingsignal and generating a second integration signal; an oscillatorgenerating a pulse signal and a ramp signal; and a feedback terminalcoupled to an output of the power supply to receive a feedback signal;wherein if the input signal is not available, the switching signal isenabled in response to the pulse signal, and is disabled in response toa comparison of the feedback signal and the ramp signal, and wherein theswitching signal is disabled once the second integration signal ishigher than the first integration signal.
 8. The switching controller asclaimed in claim 7 further comprising a resistor coupled to the inputcircuit for determining a delay time in between the input signal and thephase-shift signal.
 9. The switching controller as claimed in claim 7,wherein the time constant of the second integration circuit iscorrelated with the time constant of the first integration circuit. 10.The power sharing circuit as claimed in claim 7, wherein the firstintegration signal is increased in response to an increase of the pulsewidth of the input signal, and the pulse width of the switching signalis decreased in response to a decrease of the first integration signal.